H.265/HEVC 8K 60p Main10 Encoder

Product Overview

H.265/HEVC is the ISO/IEC standard for video compression and decompression. H.265/HEVC which has double compression performance of the H.264/AVC video compression standard, is expected to be used for high-definition video distribution such as 4K (3840 x 2160) and 8K (7680 x 4320), as well as video distribution services for mobile devices on the limited bandwidth.
We have developed and commercialized a software H.265/HEVC encoder.


  • TMC original algorithm “DMNA” made it possible the high image quality, high speed, small size and low power consumption.
  • Original parallel processing which minimizes the dispersion processing time of each core, achieves 4K (3840 x 2160) 60 frames per second real-time processing on a general-purpose PC server.
  • Processing performance is not disturbed by the memory access costs in multiprocessor environments with supporting NUMA architecture.
  • Optimized for Intel x86 and ARM Cortex-A (ARMv7 and ARMv8).
  • Supports the slice 4-division encoding method specified in the 8K format of ARIB SDT-B32.


Stream Format Byte stream format (Annex B)
Image Format YCbCr 4:2:0/4:2:2/4:4:4/4:0:0 Planar Format
Bit Depth 8 bits/10 bits/12 bits
Resolution 64 x 64 to 7680 x 4320
Operation Mode Five levels can be set at trade-off between processing speed and image quality.


This IP supports both color spaces of YCbCr and YUV.


What is NUMA architecture?

The NUMA (Non-Uniform Memory Access) architecture is one of the architectures used in shared memory multiprocessor computer systems.
It is characterized by the fact that the access speed to memory, which is shared by multiple CPUs, varies depending on the specific combination of memory and CPU.

In this architecture, there are multiple pairs of processors and memory (referred to as nodes).
The memory of the same node as a processor is called “local” memory, while the memory of other nodes is called “remote” memory.

Typically, there is a relationship where:

“access latency of local memory” < “access latency of remote memory”.

By placing frequently accessed data that processors need to access in low-cost memory and infrequently accessed data in high-cost memory, the number of processors sharing the bus is reduced, preventing bus congestion, and as a result, the bus clock improves.