The Revolutionary Algorithm DMNA Reduces CPU Load and Increases Speed of Image Processing
DMNA (Digital Media New Algorithm) is a new algorithm that dramatically reduces the computational load by using the mathematical methods such as factorization, fold operations, and hierarchical processing.
DMNA was developed by Dr. Masafumi Tanaka, a visiting professor at the University of Tokyo and his group, and its applications are not limited to moving images, but are spread to all kinds of digital media such as still images, audio, and sound.
Features of DMNA
Low power consumption
The operating frequency of the CPU has been reduced to about 1/3 of the conventional frequency, resulting in a significant reduction in power consumption.
Frame rate (number of picture pages) can be increased without increasing the operating frequency of the CPU.
High Image Quality
Our new algorithm improves image quality by 2db
Enable to process the large image sizes (high resolution) without changing the operating frequency of the CPU
Achieves a significant reduction in delay time by a hierarchical pipeline method that equalizes the delay time, which is the weakest point of digital
Advantages of TMC’s solution
An innovative algorithm, DMNA, drastically reduces the need for DCT (Discrete Cosine Transform) and ME (Motion Estimation).
Our proprietary motion detection method detects the most appropriate motion vectors to achieve high image quality even at low bit rates.
As a result of the above, high image quality can be obtained with a single pass (one time pass) encoding, which contributes to the differentiation of image quality in real-time encoding and the improvement of work efficiency in encoding for video distribution.
Since the software is developed in the standard C language, it is compatible with a wide variety of platforms, including Windows and Linux for OS, PC, DSP, and ARM for CPU. (Optimized for each platform: PC version that can use memory relatively freely, ARM version for lightness, DSP version for strong multiply-and-accumulate operations, FPGA version for reduced power consumption by reducing the number of gates, etc.)
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